Field of the Invention
The embodiments herein relate to processors and, more particularly, to implementation of data prefetch systems.
Description of the Related Art
Computing systems and processors may utilize virtualized memory techniques for various reasons, including, for example, to improve performance of memory usage, allow usage of multiple memory devices, or to increase reliability of memory cells. Virtualization of memory may include use of memory mapping tables to associate a virtual address with a physical address. When a processor operates with virtual memory, addresses used by the processor may correspond to virtual addresses that are translated into physical addresses. In other words, the virtual address may not equal the physical address (the actual address in the physical memory where information is stored).
The use of virtual addresses may allow data and program instructions to be physical relocated in a system memory by a memory controller or memory management unit. The memory controller may store the data or instructions in physical locations that provide fast access or long-term data retention. The memory controller may maintain translation tables that link a particular virtual address or range of addresses to a corresponding physical address or range of addresses. Since the memory controller maintains the translation tables, software executed by a processor does not have to be modified to reflect a current location of data and instructions in the physical memory.
The address translation process, however, may introduce additional steps for storing and retrieving information in a memory. To reduce delays due to address translations, a processor or computing system may include a translation lookaside buffer. The translation lookaside buffer stores translation information for recent memory accesses, allowing reduced access times to memory locations that are accessed more frequently.